\doxysubsubsubsection{I2C Interrupt configuration definition }
\hypertarget{group___i2_c___interrupt__configuration__definition}{}\label{group___i2_c___interrupt__configuration__definition}\index{I2C Interrupt configuration definition@{I2C Interrupt configuration definition}}


I2C Interrupt definition Elements values convention\+: 0x\+XXXXXXXX.  


\doxysubsubsubsubsubsection*{Macros}
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\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+ERRI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga75e971012a02f9dad47a1629c6f5d956}{I2\+C\+\_\+\+CR1\+\_\+\+ERRIE}}
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\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+TCI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6b37e64bdf6399ef12c3df77bcb1634f}{I2\+C\+\_\+\+CR1\+\_\+\+TCIE}}
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\Hypertarget{group___i2_c___interrupt__configuration__definition_ga0a85b2740a7d8669dfeacdc81ef0692b}\label{group___i2_c___interrupt__configuration__definition_ga0a85b2740a7d8669dfeacdc81ef0692b} 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+STOPI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1f1576cb1a2cd847f55fe2a0820bb166}{I2\+C\+\_\+\+CR1\+\_\+\+STOPIE}}
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\Hypertarget{group___i2_c___interrupt__configuration__definition_gaf64fb93453bfbae36de26ff1465029f0}\label{group___i2_c___interrupt__configuration__definition_gaf64fb93453bfbae36de26ff1465029f0} 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+NACKI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae3f71f7a55e13a467b2a5ed639e0fe18}{I2\+C\+\_\+\+CR1\+\_\+\+NACKIE}}
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\Hypertarget{group___i2_c___interrupt__configuration__definition_ga2a4058126bd3d7ea36eedfbc0f0d926d}\label{group___i2_c___interrupt__configuration__definition_ga2a4058126bd3d7ea36eedfbc0f0d926d} 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+ADDRI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga275e85befdb3d7ea7b5eb402cec574ec}{I2\+C\+\_\+\+CR1\+\_\+\+ADDRIE}}
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\Hypertarget{group___i2_c___interrupt__configuration__definition_ga37af8a13ac5afcbd22cec22f471543ce}\label{group___i2_c___interrupt__configuration__definition_ga37af8a13ac5afcbd22cec22f471543ce} 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+RXI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf1fc89bf142bfc08ee78763e6e27cd80}{I2\+C\+\_\+\+CR1\+\_\+\+RXIE}}
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\Hypertarget{group___i2_c___interrupt__configuration__definition_gae0ed342e48cfd545190da23791980c35}\label{group___i2_c___interrupt__configuration__definition_gae0ed342e48cfd545190da23791980c35} 
\#define {\bfseries I2\+C\+\_\+\+IT\+\_\+\+TXI}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8bd36da8f72bc91040e63af07dd6b5a4}{I2\+C\+\_\+\+CR1\+\_\+\+TXIE}}
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\doxysubsubsubsubsection{Detailed Description}
I2C Interrupt definition Elements values convention\+: 0x\+XXXXXXXX. 


\begin{DoxyItemize}
\item XXXXXXXX \+: Interrupt control mask 
\end{DoxyItemize}